TweakTown

Phison intros new E37T Gen5 SSD controller: up to 14.7GB/sec reads, DRAM-less, under 2.3W power

Phison's new PS5037-E37T revealed at CES 2026: new Gen5 SSD controller, DRAM-less, TSMC 6nm process, less than 2.3W power, up ...
cbswatchmagazine

Phison Unveils E37T Gen5 SSD Controller: Blazing 14.7 GB/s Speeds in a DRAM-Less, Energy-Efficient Design

Phison has unveiled its latest innovation at CES, the Gen5 SSD controller known as the E37T. This new controller is crafted ...
Guru3D

Phison Introduces E37T PCIe Gen 5 Controller for Efficient Mobile SSDs

Phison has announced the E37T PCIe Gen 5 controller, expanding its storage controller portfolio toward more efficient and compact consumer devices. While first-generation PCIe Gen 5 SSDs largely ...
Hackaday

dram controller

Ask anyone to name a first-generation home computer from the 1970s, and they’ll probably mention the likes of the Altair 8800 and IMSAI 8080. But those iconic machines weren’t the only options ...
TweakTown

Phison's new PS5031-E31T: world's first DRAM-less Gen5 SSD controller, up to 10.8GB/sec

The company says that its new PS5031-E31T Gen5 SSD controller is essential in making Gen5 SSDs more cost-efficient, with some things tweaked that will result in cheaper Gen5 SSDs in the near future.
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
Hosted on MSN

Realtek eyes SSDs with new PCIe 5.0 x4 DRAM-less controller — Up to 10 GB/s and 1.4M IOPS

Realtek is typically associated with audio, multimedia, and networking controllers for budget PCs, but for several years, the company has been trying to enter the SSD controller market, challenging ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
EDN

NEC adds L2 cache, DRAM controller to Vr processor

SANTA CLARA, Calif. — NEC Corp. has taken the wraps off a MIPS-based 64-bit embedded processor that integrates Level 2 cache and a DRAM controller, both equipped with error-correction coding features.