EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
Electronic Design

15V, Dual 3A Monolithic Synchronous Step-Down Regulator Powers DDR1, DDR2 or DDR3 Memory

The LTC3634 is a high efficiency, dual-channel monolithic synchronous step-down regulator from Linear Technology, which provides power supply and bus termination rails for DDR1, DDR2 and DDR3 SDRAM ...
Design-Reuse

Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design

High performance DDR2 SDRAM is an increasingly common memory solution for designs requiring improved data bandwidth capabilities, lower power, and enhanced signaling features. However, the benefits of ...
Ars Technica

MetaRAM quadruples DDR2 DIMM capacities, launches 8GB DIMMs

Since its launch in January 2006, the only thing that has been publicly known about former AMD CTO Fred Weber's new venture is its name: MetaRAM. Clearly, the stealth-mode company was working on ...
EDN

Designing DDR3 SDRAM controllers with today’s FPGAs

The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet ...
Design-Reuse

The Love/Hate Relationship with DDR SDRAM Controllers

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write this article. In fact, approximately 90% of all DRAMs produced are used in ...