Custom PC Review

Intel Details 10nm FinFET Process: Boasts 25% Improved Performance, 45% Better Power Efficiency, 2.7x Increased Transistor Density

At Intel’s recent Technology and Manufacturing Day, Intel presented more details regarding its 10nm FinFET manufacturing process. In the presentation materials, Intel highlighted some of the major ...
Semiconductor Engineering

Low Power Trends Toward FinFET

Survey shows nearly a third of all designs are targeting the most advanced process nodes; 10nm tapeouts will happen right on the heels of 14/16nm. My previous blog, Power Reduction Techniques, covered ...
Design-Reuse

Cadence Announces Tapeout of 14nm Test-chip with ARM Processor and IBM FinFET Process Technology

14-nanometer SOI FinFET Process Leverages Strong Ecosystem Partnerships Between EDA, Foundry and IP Providers to Deliver Significant Power Savings Potential SAN JOSE, Calif., 30 Oct 2012 - Cadence ...
Semiconductor Engineering

Variation In Low-Power FinFET Designs

One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation ...
Design-Reuse

Synopsys and UMC Collaborate to Accelerate Development of UMC's 14-nm FinFET Process

HSINCHU, Taiwan and MOUNTAIN VIEW, Calif. -- June 26, 2013 -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic ...
EDN

All you need to know about GAA chip manufacturing process

The gate-all-around (GAA) semiconductor manufacturing process, also known as gate-all-around field-effect transistor (GAA-FET) technology, defies the performance limitations of FinFET by reducing the ...